Timing Diagram Lecture

Unified Modeling Language

The Unified Modeling Language (UML) is a general-purpose, developmental, modeling language in the field of software engineering that is intended to provide a standard way to visualize the design of a system.

The creation of UML was originally motivated by the desire to standardize the disparate notational systems and approaches to software design. It was developed at Rational Software in 1994–1995, with further development led by them through 1996.

In 1997, UML was adopted as a standard by the Object Management Group (OMG), and has been managed by this organization ever since. In 2005, UML was also published by the International Organization for Standardization (ISO) as an approved ISO standard. Since then the standard has been periodically revised to cover the latest revision of UML. In software engineering, most practitioners do not use UML, but instead produce informal hand drawn diagrams; these diagrams, however, often include elements from UML.

Timing Diagram

A timing diagram in the Unified Modeling Language 2.0 is a specific type of interaction diagram, where the focus is on timing constraints.

Timing diagrams are used to explore the behaviors of objects throughout a given period of time. A timing diagram is a special form of a sequence diagram. The differences between timing diagram and sequence diagram are the axes are reversed so that the time increases from left to right and the lifelines are shown in separate compartments arranged vertically.

There are two basic flavors of timing diagram: the concise notation, and the robust notation.

Lecture objectives: at the end of this lecture the student will able to:

1- Define the timing diagram.

2- Study and representation of the clock signal.

3- Determine the types of 8085 machine cycles.

9.1 Some of Definitions:

9.1.1 Timing Diagram: Timing diagram is the display of initiation of read/write and transfer of data operations under the control of 3-status signals IO / M , S1, and S0.

9.1.2 Instruction Cycle: It is fetching, decoding and executing of a single instruction, which consists of one to five read or writing operations between processor and memory or IO devices.

9.1.3 Machine Cycle: It is the one cycle that required to move one byte of data in or out of the microprocessor. Each one machine cycle consists 3 to 6 clock period, referred to as T-state.

9.1.4 T-state: It is the time of one clock period which depends on operating frequency. Another definition of the T-state is a portion of an operation carried out in one system clock period. There are seven different types of machine cycles in 8085A. Table 9.1 show these types which its identified depend on status signals IO / M , S1, and S0. These signals are generated at the beginning of each machine cycle and remained valid for the duration of the cycle.

9.2 Clock Signal: The 8085 divide the clock frequency provided by X1 and X2 inputs by 2 which is called operating frequency. Ideally, the clock signals should be square wave with zero rise time and fall time, but practically, cannot get zero rise time and fall time.